Memory storage is a constantly advancing field, as there is continued demand for larger memory capacities, at lower cost, lower power consumption per unit of storage and faster storage and retrieval speeds. There are different technologies that are in common use.
Storage of digital data as capacitive charges in a dynamic memory structure is well represented in the literature. Optimized logic design, innovative physical structures, and targeted semiconductor process improvements have been applied to create high density, high performance dynamic memory components of significant performance, capacity, and economy. Thus, the particular semiconductor technology used for large memory chips, such as dynamic random access memory (DRAM) chips, has been the topic of much research and DRAM technologies have been highly refined.
However, there is also a demand for comparatively small amounts of memory within, for example, a custom or semi-custom semiconductor logic device that uses a different technology. As such devices are based on different semiconductor processes and layout rules than are used to create DRAM devices, few of the optimizations developed for dedicated DRAMs are applicable to these embedded memory designs. Instead, the memory portions of such devices typically rely on planar capacitive structures of relatively low capacitance and relatively large area. Use of such relatively low capacitance, non-optimized cells can result in reduced signal output on a read operation, since readout of the stored charge is divided between the lower cell capacitance and the relatively fixed sense line parasitic capacitance. Mitigation of this effect requires the use of larger storage elements, significantly increasing the semiconductor area required for the embedded storage array.
As a result, improvements in structural design of memory would be useful.